ASICS (Application Specific Integrated Circuits) can be used to manipulate and/or to monitor data streams. Within such ASICS there are typically circuits and functional blocks which generate short pulse-shaped status or error indications. Furthermore, the ASICS must update a latch register as soon as the indication was fetched from the hardware device. As already mentioned above, a register or flip-flop latching the status indication (e.g. a bit) operates in a different clock domain than the circuitry processing the latched indication (e.g. a microcontroller interface). Consequently, a synchronization functionality is needed to avoid metastability when accessing the latch register.
Metastability can occur if the setup-hold window of a flip-flop (FF) is violated. When metastability occurs the logical state of the FF output can not be predicted and furthermore the exact point of time at which the undefined logical value settles to a defined state can only be given to a certain probability of error. Of course, in principle even a metastable flip-flop can be read out. However, it is completely uncertain which logical value is read out due the metastability.
Furthermore, the synchronization and update functionality must not overlap the detection of an error indication, even if the update request and a new indication coincide in time.
A typical environment where there is need for latching such status indication is for example in the framework of SONET/SDH applications. For such an application a circuitry shall latch short, clock cycle long indications, synchronize them to a microcontroller interface and provide an update at read functionality, while not covering new indications during the read and update phase. For example, a SDH/SONET ASIC shall receive, monitor and process potentially 16 SDH/SONET data steams. In this case, clocks are recovered from the data steams in SDH/SONET applications and therefore the ASIC involves 16 clock domains with the same nominal clock frequency but unpredictable phase relationship amongst each other and to the microcontroller interface which enables a controlling and configuring controller to access the latched indications. The latched indications are supposed to be available until the microcontroller reads them and thereby updates them to the new indication status not covering indications that came in during the read out phase. Therefore, by only two consecutive read accesses the microcontroller is able to detect a change in the indication status.